1. Field of the Invention
This invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having an on-chip test circuit, and the method for testing the semiconductor memory device.
2. Description of Background Art
Memory test time has been increasing with packing density. Especially, functional test time occupies a large part of the total test time in high packing density memories. In general, memory functions are tested using test patterns whose length is increasing with memory capacity N. Test patterns for memories can be classified into N.sup.2, N.sup.3/2, and N patterns according to their pattern length. The N patterns test memories by writing data into all cells and reading them. Though pattern lengths are different in their address and data sequences, they are proportional to N. The N.sup.2 pattern can detect all interference effect between any two cells. The N.sup.3/2 pattern can test interference effect between two cells connected to the same word or bit line. Though N.sup.2 or N.sup.3/2 patterns are suitable for testing pattern sensitivity of memory cells, test time using them is too long for practical use. In testing a 1 Mb memory chip at 500 ns cycle time, it takes about 9 minutes per chip to test using the N.sup.3/2 pattern. As this is not practical, N patterns are usually applied to test mega-bit level memories to reduce test time. In this case, test time is about 5 seconds using a 10N cycle Marching pattern. Though N patterns have been used so far, it will be difficult to apply even them in testing larger capacity memories.
Several methods have been reported on reduction of memory test time by testing cells in parallel. In testing DRAMs, test time reduction by testing four bits simultaneously, called multi-bit test, was reported. Also reported was a parallel test using a linear feedback shift register as a parallel signature analyzer.sup.2.
With increase in the capacity of the semiconductor memory device, the problem of prolonged testing time has been presented as a serious problem. Thus a line mode testing method has been proposed as the method whereby the testing may be shortened significantly. According to this line mode testing method, all of the memory cells connected to a given word line can be tested simultaneously. These results in significant reduction of the testing time.
FIG. 7 is a block diagram showing the structure of the conventional dynamic random access memory (referred to hereinafter as a dynamic RAM) which is equipped with an on-chip testing circuit for line mode testing.
In a memory cell array 1 of FIG. 7, a plurality of word lines and a plurality of bit line pairs are arranged to intersect one another. A plurality of memory cells are provided at intersections thereof. The word lines in the memory cell array 1 are connected to a row decoder 3 by way of a word driver 2. The bit line pairs in the memory cell array 1 are connected to a column decoder 6 by way of a sense amplifier section 4 and an I/O switch 5.
A RAS buffer 7 is responsive to a row address strobe signal RAS supplied from outside to activate a row address buffer 8. The row address buffer 8 functions to latch an address signal A supplied from outside to supply it as a row address signal RA to the row decoder 3. The row decoder 3 is responsive to the row address signal RA to select one of the word lines to drive the selected word line by way of the word driver 2. Information in the memory cells connected to the driven word line is read out on corresponding bit line pairs, respectively. The sense amplifier 4 functions to sense and amplify the information on the bit line pairs.
On the other hand, a CAS buffer 9 is responsive to a column address strobe signal CAS supplied from outside to activate a column address buffer 10. The column address buffer 10 functions to latch the address signal A supplied from outside to supply it as a column address signal CA to the column decoder 6. The column decoder 6 is responsive to the column address signal CA to select one of the bit line pairs to connect the selected bit line pair to an input/output line pair I/O, I/O. In this manner, one of the word lines and one of the bit line pairs are selected so that information is read out or written from or to the memory cell at the intersection thereof. FIG. 7 shows only the selected word line WL, the selected bit line BL and the memory cell MC at the intersection thereof.
Information read-out or writing is selected by a read/write buffer 11. The read/write buffer 11 is responsive to a read/write signal R/W supplied from outside to activate an input buffer 12 or an output buffer 13. When the input buffer 12 is activated, an input data Din is written in the thus selected memory cell MC. When the output buffer 13 is activated, the information stored in the thus selected memory cell MC is read out as an output data Dout to outside.
A write circuit 14, a comparator circuit 15, a detection circuit 16 and a line test controller 17 are used for line mode testing. The line test controller 17 is responsive to a test enable signal TE supplied from outside to control the write circuit 14, the comparator circuit 15 and the detection circuit 16. The above described components 1 to 17 of the dynamic RAM are formed on one and the same chip 100.
FIG. 8 shows a detailed circuit diagram of essential portions of the dynamic RAM shown in FIG. 7. The circuit of FIG. 8 is disclosed in, for example, a lecture No. 165 of pre-papers for Electronic Information Communication Society, Branch of Semiconductor Materials 1987, entitles "Technology for Improving Testing Efficiency Suitable for Large Capacity Memories". The circuit of FIG. 8 is also disclosed in the Japanese Patent Laying-Open No. 63-102094.
In FIG. 8, only two sets of bit line pair BL1, BL1 and BL2, BL2 and four word lines WL1 to WL4, are shown. A sense amplifier 40 is connected to each of the bit line pairs BL1, BL1 and BL2, BL2. The bit line pair BL1, BL1 is connected to the input line pair I/O, I/O by way of transistors Q9, Q10, while the bit line pair BL2, BL2 is connected to the input/output line pair I/O, I/O by way of transistors Q11, Q12. Column select signals C1 and C2 are supplied from the column decoder 6 of FIG. 7 to the gates of the transistors Q9 and Q10 and the gates of the transistors Q11, Q12, respectively.
The write circuit 14 includes transistors Q1 to Q4, write lines W and W and a write control line WC. The comparator circuit 15 includes transistors Q5 to Q8 and the detection circuit 16 includes a precharge circuit 160, transistors S1 and S2 and an inverter G1.
The line mode testing method is hereinafter explained by referring to a waveform diagram of FIG. 9. In line mode testing, parallel writing and parallel comparison are performed.
For parallel writing, the potential at the word line WL1, for example, is raised to logically high level ("H" level). Desired testing data are then applied to the write lines W and W. When logical high (or "H") is to be written as a testing data, an "H" level data and a logically low level data (an "L" level data) are applied to the write line W and W, respectively. With the potential at the write control line WC raised to the "H" level, the transistors Q1 to Q4 are rendered conductive. This allows the potential at the write line W to be transmitted to the bit lines BL1 and BL2, and the potential at the write line W to be transmitted to the bit lines BL1 and BL2. The potential difference between the bit lines BL1 and BL1 and the potential difference between the bit lines BL2 and BL2 are sensed and amplified by sense amplifiers 40. In this manner, test data are written simultaneously in all of the memory cells connected to the word line WL1. In FIG. 8, an "H" level data are written in the memory cells MC1 and MC3.
On the other hand, during parallel comparison, the potential at the write control line WC is maintained at the logically low level. That is, with the transistors Q1 to Q4 non-conductive, the word line WL1 is selected so that the potential at the word line WL1 is raised to the "H" level. This allows the data stored in the memory cells MC to MC3 to be read out on the bit lines BL1 and BL2. The potential difference between the bit lines BL1 and BL1 and the potential difference between the bit lines BL2 and BL2 are sensed and amplified by the sense amplifiers 40. Data opposite to those written during the above writing is supplied to the write lines W, W as the expected data. That is, data at the "L" level is supplied to the write line W, while data at the "H" level are supplied to the write line W.
If the data stored in the memory cells MC1 and MC3 are read out correctly, the potentials at the bit lines BL1 and BL2 are raised to the "H" level, while the potentials at the bit lines BL1 and BL2 are lowered to the "L" level. As a result, the transistors Q5 and Q7 are rendered conductive, while the transistors Q6 and Q8 are rendered non-conductive, so that the "L" level potential at the write line W is transmitted to nodes N1 and N2. This renders transistors S1 and S2 non-conductive. Thus the potential at the node N1, which has been precharged to the "H" level by the precharge circuit 160, remains at the "H" level, so that the potential at a detection result output line F remains at the "L" level.
It is now assumed that the data stored in the memory cell MC1 has been read out incorrectly by some reason or other. In this case, the potential at the bit line BL1 goes to the "L" level, while the potential at the bit line BL1 goes to the "H" level. This renders the transistor Q5 non-conductive and the transistor Q6 conductive. As a result, the "H" level potential at the write line W is transmitted to the node N1 to render the transistor S1 conductive. Thus the potential at the node N1, which has been precharged to the "H" level by the precharge circuit 160, is discharged to the "L" level by way of the transistor S1. As a result, an "H" level signal appears on the detection result output line F.
In this manner, when all of the bits at the memory cells connected to the selected word line are normal, an "L" level signal appears on the detection result output line F. Conversely, if even one of the bits at the memory cells connected to the selected word line is in error, an "H" level signal appears on the detection result output line F. Thus the possible troubles of the memory cells may be determined for a word line.
The above described line mode testing is performed for all of the word lines to complete the testing for the totality of the memory cells. With the above described line mode testing, all of the memory cells connected to a word line can be tested simultaneously to permit significant shortening in the testing time.
In this case, since the row including a defective memory cell is replaced with a redundancy circuit, it is not necessary to specify the defective memory cell.
However, the large capacity semiconductor memory devices are subject to various failure modes besides the defects of the memory cells. For example, so-called a Y line failure, that is the trouble along the bit lines, may be produced due to bit line shorting or breakage or troubles in the sense amplifiers. When the above described conventional line mode testing method is applied to the semiconductor memory device suffering from the Y line failure, negative detection results will be issued for all of the word lines. Thus it cannot be determined whether the trouble is that of all bits of the memory cells or the Y line failure. Also, should the Y line failure exist, it is not possible to locate the Y line failure.
In the memory cell array comprising a plurality of memory cells MC as shown in FIG. 10, if it is possible to specify the column CY in which Y line failure exists, the column CY can be replaced with a redundancy circuit R comprising spare memory cells SMC.